1. Field of the Invention
The present invention generally relates to a nonvolatile memory device using a serial diode cell, and more specifically, to a technology of providing a plurality of sub cell arrays each as a cross point cell having in a hierarchical bit line structure including a main bit line and a sub bit line, thereby reducing the whole size of a chip.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FeRAM are disclosed in the Korean Patent Application No. 2001-57275 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein.
A unit cell of the conventional FeRAM comprises a switching device and a nonvolatile ferroelectric capacitor which is connected between one terminal of the switching device and a plate line. The switching device performs a switching operation depending on a state of a word line to connect the nonvolatile ferroelectric capacitor to a sub bit line.
Here, the switching device of the conventional FeRAM is generally a NMOS transistor whose switching operation is controlled by a gate control signal. However, when a cell array is embodied by using the above-described NMOS transistor as a switching device, the whole chip size increases.
As a result, it is necessary to embody a sub cell array comprising the above-described nonvolatile ferroelectric memory device and a serial diode switch which does not require an additional gate control signal as a cross point cell having a hierarchical bit line structure including a main bit line and a sub bit line.